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MK31VT464-10YE (98.07.24) page 1/11 semiconductor MK31VT464-10YE 4,194,304 word x 64 bit synchronous dynamic ram module (1bank): description the oki MK31VT464-10YE is a fully decoded, 4,194,304 x 64bit synchronous dynamic random access memory composed of four 64mb drams (4mx16) in tsop packages mounted with decoupling capacitors on a 144-pin glass epoxy small-outline dual-in-line package supports any application where high density and large capacity of storage memory are required, like for example mobile pc or pdas. features 4-meg word x 64-bit (1bank 8byte) organization 144-pin small-outline dual inline memory module single 3.3v power supply, 0.3v tolerance input :lvttl compatible output :lvttl compatible refresh : 4,096 cycles / 64 ms programmable data transfer mode ? /cas latency (2, 3) ? burst length (2, 4, 8) ? data scramble (sequential, interleave) /cas before /ras auto-refresh, self-refresh capab ility serial presence detect (spd) with eeprom product organization operation access time (max.) product name frequency (max.) t ac2 t ac3 MK31VT464-10YE 100 mhz 9.0ns 9.0ns note. specification are subject to change without notice.
MK31VT464-10YE (98.07.24) page 2/11 block diagram 2 4 clk0 13 clk1 / cs0 cke0 dqmb0 dqmb4 dq0 dq7 dq8 dq15 dqmb1 udqm dq40 dq47 dqmb5 dqmb2 dqmb6 dq0 dq7 dq16 dq23 dq0 dq7 dq48 dq55 dqmb7 dq0 dq7 dq24 dq31 dq0 dq7 dq56 dq63 dqmb3 dq0 dq7 ldqm cke / cs dq32 dq39 vcc vss sdrams 0.22uf x4 / ras,/cas,/we a0-a11,ba0,ba1 14 scl sda a0 a1 a2 serial pd 10pf 1 5 dq15 dq8 udqm ldqm cke / cs udqm dq0 dq7 ldqm cke / cs 2 dq15 dq8 udqm ldqm cke / cs 4 3 dq0 dq7 dq15 dq8 dq0 dq7 dq15 dq8 note. the value of all resistors is 10 w . module outline (front) (back) 1 2 59 60 61 62 143 144
MK31VT464-10YE (98.07.24) page 3/11 pin configuration fr o nt b ac k s i de fr o nt s i de b ac k s i de pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 vss 2 vss 73 n.c 74 clk1 3 dq0 4 dq32 75 vss 76 vss 5 dq1 6 dq33 77 n.c 78 n.c 7 dq2 8 dq34 79 n.c 80 n.c 9 dq3 10 dq35 81 vcc 82 vcc 11 vcc 12 vcc 83 dq16 84 dq48 13 dq4 14 dq36 85 dq17 86 dq49 15 dq5 16 dq37 87 dq18 88 dq50 17 dq6 18 dq38 89 dq19 90 dq51 19 dq7 20 dq39 91 vss 92 vss 21 vss 22 vss 93 dq20 94 dq52 23 dqmb0 24 dqmb4 95 dq21 96 dq53 25 dqmb1 26 dqmb5 97 dq22 98 dq54 27 vcc 28 vcc 99 dq23 100 dq55 29 a0 30 a3 101 vcc 102 vcc 31 a1 32 a4 103 a6 104 a7 33 a2 34 a5 105 a8 106 ba0 35 vss 36 vss 107 vss 108 vss 37 dq8 38 dq40 109 a9 110 ba1 39 dq9 40 dq41 111 a10 112 a11 41 dq10 42 dq42 113 vcc 114 vcc 43 dq11 44 dq43 115 dqmb2 116 dqmb6 45 vcc 46 vcc 117 dqmb3 118 dqmb7 47 dq12 48 dq44 119 vss 120 vss 49 dq13 50 dq45 121 dq24 122 dq56 51 dq14 52 dq46 123 dq25 124 dq57 53 dq15 54 dq47 125 dq26 126 dq58 55 vss 56 vss 127 dq27 128 dq59 57 n.c 58 n.c 129 vcc 130 vcc 59 n.c 60 n.c 131 dq28 132 dq60 61 clk0 62 cke0 133 dq29 134 dq61 63 vcc 64 vcc 135 dq30 136 dq62 65 /ras 66 /cas 137 dq31 138 dq63 67 /we 68 n.c 139 vss 140 vss 69 /cs0 70 n.c 141 sda 142 scl 71 n.c 72 n.c 143 vcc 144 vcc pin name function pin name function vcc power supply (3.3v) /ras row address strobe vss ground (0v) /cas column address strobe clk# system clock /we write enable /cs# chip select dqmb# data input / output mask cke# clock enable dq# data input / output a0-a11 address sda data i/o for spd ba0,ba1 bank select address scl clk input for spd n.c no connection
MK31VT464-10YE (98.07.24) page 4/11 serial presence detect byte no. spd hex value remark notes 0 80 defines the number of bytes written into spd memory 128 byte 1 08 total number of bytes of spd memory 256 byte 2 04 fundamental memory type sdram 3 0c number of rows 12 rows 4 08 number of columns 8 columns 5 01 number of module banks 2 bank 6 40 data width of this assembly 64 bits 7 00 ... data width conti nuation 0 bits 8 01 voltage interface level lvttl 9 a0 cycle time (cl=3) cl=3 t cc =10ns 10 90 access time from clk (cl=3) cl=3 t ac3 =9ns 11 00 dimm configuration type non parity 12 80 refresh rate / type normal / self 13 10 primary sdram width x16 14 00 error checking sdram width 15 01 minimum clk delay t ccd : 1 clk 16 0e burst lengths supported 2,4,8 17 04 number of banks on each sdram 4 banks 18 06 /cas latency 2,3 19 01 /cs latency 0 20 01 /we latency 0 21 00 sdram module attributes 22 06 sdram device attributes : general 23 f0 cycle time (cl=2) cl=2 t cc2 =15ns 24 90 access time from clk (cl=2) cl=2 t ac2 =9ns 25 00 cycle time (cl=1) not support 26 00 access time from clk (cl=1) not support 27 1e minimum row pulse width t rp =30ns 28 14 /ras to /ras bank delay t rrd =20ns 29 1e /ras to /cas delay t rcd =30ns 30 3c minimum /ras precharge time t ras =60ns 31 08 density of each bank on module 32mb 32 30 command and address signal input setup time 3ns 33 10 command and address signal input hold time 1ns 34 30 data signal input setup time 3ns 35 10 data signal input hold time 1ns 36-61 00-00 r.f.u 62 02 spd data revision code 0.2 63 59 checksum for byte 0-62 64-71 41,45,20,20,20,20,20,20 manufacturers jedec id code 72 01 / 06 manufacturing location 73-90 4d,4b,33,31,56,54,34,36,34, 2d , 31 , 30 , 59 , 45 , 20 , 20 , 20 , 20 manufacturers part number MK31VT464-10YE 91,92 20,20 revision code 93-125 00-00 r.f.u 126 66 intel specification frequency 66mhz 127 06 intel specification /cas latency cl=2, 3 128-255 ff-ff unused storage locations
MK31VT464-10YE (98.07.24) page 5/11 electrical characteristics absolute maximum ratings rating symbol value unit voltage on any pin relative to vss v in , v out -0.5 to vcc + 0.5 v vcc supply voltage v cc , v cc q -0.5 to 4.6 v storage temperature t stg - 55 to 125 c power dissipation p d* 4w short circuit current i os 50 ma operating temperature t opr 0 to 70 c *: ta=25 c recommended operating conditions (voltages referenced to vss = 0v) parameter symbol min. typ. max. unit power supply voltage vcc, vccq 3.0 3.3 3.6 v input high voltage v ih 2.0 - vcc + 0.3 v input low voltage v il -0.3 - 0.8 v capacitance (vcc = 3.3v 0.3 v , ta = 25c f = 1mhz) parameter symbol max. unit input capacitance(a0-a11, ba0, ba1) c in1 20 pf input capacitance(/cs0, /ras, /cas, /we, cke0, udqm, ldqm) c in2 20 pf i/o c apacitance(dq0 - dq63 ) c i/o 28 pf
MK31VT464-10YE (98.07.24) page 6/11 dc characteristics (vcc = 3.3v 0.3v, ta = 0 to 70c) condition module spec. parameter symbol cke others min. max. unit note output high voltage v oh -i oh = -2.0ma 2.4 - v output low voltage v ol -i ol = 2.0ma -0.4v input leakage current i li - - -40 40 m a output leakage current i lo - - -20 20 m a average power supply current (operating) i cc 1 cke 3 v ih t cc =min. t rc =min. no burst - 580 ma 1, 2 power supply current (stand by) i cc 2 cke 3 v ih t cc =min. - 160 ma 3 average power supply current (clock suspension) i cc 3s cke v il t cc =min. -60 ma 2 average power supply current (active stand by) i cc 3 cke 3 v ih , /cs 3 v ih t cc =min. - 380 ma 3 power supply current (burst) i cc 4 cke 3 v ih t cc =min. - 840 ma 1, 2 power supply current (auto-refresh) i cc 5 cke 3 v ih t cc =min. t rc =min . - 740 ma 2 average power supply current (self-refresh) i cc 6 cke 0.2v t cc =min. -8 ma average power supply current (power down) i cc 7 cke v il t cc =min. - 328 ma notes: 1. measured with the output open. 2. address and data can be changed once or not be changed during one cycle. 3. address and data can be changed once or not be changed during two cycle. mode set address keys /cas latenc y burst t y pe burst len g th a6 a5 a4 cl a3 bt a2 a1 a0 bt=0 bt=1 0 0 0 reserved 0 se q uential 0 0 0 reserved reserved 0 0 1 reserved 1 interleave 0 0 1 2 2 010 2 010 4 4 011 3 011 8 8 1 0 0 reserved 1 0 0 reserved reserved 1 0 1 reserved 1 0 1 reserved reserved 1 1 0 reserved 1 1 0 reserved reserved 1 1 1 reserved 1 1 1 reserved reserved note: a7, a8, a9, a10, a11, ba0, ba1 and all should stay "l" during mode set cycle.
MK31VT464-10YE (98.07.24) page 7/11 power on sequence 1. with inputs in nop state, turn on the power supply and enter the system clock. 2. after the vcc voltage has reached the specified level, take a pause of 200 m s or more with the input being nop. 3. enter the precharge all bank command. 4. apply cbr auto-refresh eight or more times. 5. enter the mode register setting command.
MK31VT464-10YE (98.07.24) page 8/11 ac characteristic (v cc = 3.3v 0.3v, ta = 0 ~ 70c) note 1, 2 . parameter symbol m odule spec. unit note min. max. clock cycle time cl=3 t cc 10 - ns cl=2 15 - ns access time from clock cl=3 t ac - 9 ns 3, 4 cl=2 - 9 ns 3, 4 clock "h" pulse time t ch 3-ns clock "l" pulse time t cl 3-ns input setup time t si 3-ns input hold time t hi 1-ns output low impedance time from clock t olz 3-ns output high impedance time from clock t ohz -8ns output hold from clock t oh 3-ns3 /ras cycle time t rc 90 - ns /ras precharge time t rp 30 - ns /ras active time t ras 60 1,000,000 ns /ras to /cas delay time t rcd 30 - ns write recovery time t wr 15 - ns /ras to /ras bank active delay time t rrd 20 - ns refresh time t ref -64ms power-down exit set-up time t pde t si + 1clk -ns input level transition time t t -3ns /cas to /cas delay time (min) i ccd 1 cycle clock disable time from cke i cke 1 cycle data output high impedance time from i doz 2 cycle data input mask time from dqmb i dod 0 cycle data input time from write command i dwd 0 cycle data output high inpedancetime from precharge command i roh 2 cycle active command input time from mode i mrd 3 cycle write command input time from output i owd 2 cycle notes: 1) ac measurements assume t t =1ns. 2) the reference level for timing of input signals is 1.4v. 3) this parameter is measured with a load circuit equivalent to 1 ttl load and 50pf (r load is 50ohm). 4) an access time is measured at 1.4v. 5) if t t is longer than 1ns, the reference level for timing of input signals are v ih and v il . output 50pf output load 50 w 1.4v
MK31VT464-10YE (98.07.24) page 9/11 function truth table (table1) (1/2) current state /cs /ras /cas /we ba addr action idle h x x x x x nop lhhhxxnop l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra row active l l h l ba a10 nop 4 l l l h x x auto-refresh or self-refresh 5 l l l l l op code mode register write row active h x x x x x nop lhhxxxnop l h l h ba ca, a10 read l h l l ba ca, a10 write l l h h ba ra illegal 2 l l h l ba a10 precharge lllxxxillegal read h x x x x x nop (continue row active after burst ends) l h h h x x nop (continue row active after burst ends) l h h l ba x burst stop l h l h ba ca, a10 term burst, start new burst read 3 l h l l ba ca, a10 term burst, start new burst write 3 l l h h ba ra illegal 2 l l h l ba a10 term burst, execute row precharge lllxxxillegal write h x x x x x nop (continue row active after burst ends) l h h h x x nop (continue row active after burst ends) l h h l ba x burst stop l h l h ba ca, a10 term burst, start new burst read 3 l h l l ba ca, a10 term burst, start new burst write 3 l l h h ba ra illegal 2 l l h l ba a10 term burst, execute row precharge 3 lllxxxillegal read with h x x x x x nop (continue burst to end and enter row precharge) auto precharge l h h h x x nop (continue burst to end and enter row precharge) l h h l ba x illegal 2 l h l h ba ca, a10 illegal 2 l h l l x x illegal l l h x ba ra, a10 illegal 2 lllxxxillegal write with h x x x x x nop (continue burst to end and enter row precharge) auto precharge l h h h x x nop (continue burst to end and enter row precharge) l h h l ba x illegal 2 l h l h ba ca, a10 illegal 2 l h l l x x illegal l l h x ba ra, a10 illegal 2 lllxxxillegal
MK31VT464-10YE (98.07.24) page 10/11 function truth table (table1) (2/2) current state /cs /ras /cas /we ba addr action precharge h x x x x x nop ? idle after t rp lhhhxxnop ? idle after t rp l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a10 nop 4 lllxxxillegal write h x x x x x nop recovery l h h h x x nop l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a10 illegal 2 lllxxxillegal row active h x x x x x nop row active after t rcd l h h h x x nop row active after t rcd l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a10 illegal 2 lllxxxillegal refresh h x x x x x nop ? idle after t rc lhhxxxnop ? idle after t rc l h l x x x illegal l l h x x x illegal lllxxxillegal auto resister h x x x x x nop access l h h h x x nop l h h l x x illegal l h l x x x illegal l l x x x x illegal abbreviations ra = row address ba = bank address nop = no operation command ca = column address ap = auto precharge notes: 1. all inputs will be enabled when cke is set high for at least 1 cycle prior to the inputs. 2. illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. satisfy the timing of t ccd and t wr to prevent bus contention. 4. nop to bank precharging or in idle state. precharges activated bank by ba or a10. 5. illegal if any bank is not idle.
MK31VT464-10YE (98.07.24) page 11/11 function truth table (cke) (table2) current state(n) cken-1 cken /cs /ras /cas /we addr action self refresh h x x x x x x invalid l h h x x x x exit self refresh ? abi l h l h h h x exit self refresh ? abi l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain self refresh) power down h x x x x x x invalid l h h x x x x exit power down ? abi l h l h h h x exit power down ? abi l h l h h l x illegal l h l h l x x illegal l h l x x x x illegal 6 l l x x x x x nop (continue power down mode) all banks idle 6 h h x x x x x refer to table 1 (abi) h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l h l x illegal h l l l l h x enter self refresh h l l l l l x illegal llxxxxxnop any state h h x x x x x refer to operations in table 1 other than h l x x x x x begin clock suspend next cycle listed above l h x x x x x enable clock of next cycle l l x x x x x continue clock suspension notes: 6. power-down and self refresh can be entered only when all the banks are in an idle state.

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